David Nminibapiel

Intel (United States)

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Helmut Baumgart

Thomas Jefferson National Accelerator Facility

Pragya R. Shrestha

Theiss Research

Kin P. Cheung

Center for Nanoscale Science and Technology

J. P. Campbell

National Institute of Standards and Technology

Madhavi Tangirala

Old Dominion University

Vladimir Kochergin

MicroXact (United States)

Dmitry Veksler

HRL Laboratories (United States)

Jason T. Ryan

National Institute of Standards and Technology

Kai Zhang

University of Göttingen

Christian Kübel

Karlsruhe Institute of Technology

Cooperative Institutions

Intel (United States)

Old Dominion University

National Institute of Standards and Technology

Dominion University College

National Institute of Standards

Thomas Jefferson National Accelerator Facility

Physical Measurement Laboratory

Pennsylvania State University

IMEC

Arizona State University

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Compliance-Free Pulse Forming of Filamentary RRAM

Pragya R. Shrestha David Nminibapiel Jihong Kim Helmut Baumgart Kin P. Cheung

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Citations (2)

Method to evaluate off-state breakdown in scaled Tri-gate technologies

2022 IEEE International Reliability Physics Symposium (IRPS) (2022)

David Nminibapiel K. Joshi R. Ramamurthy L. Pantisano Inanc Meric

The source-drain punch-through current in off-state TDDB stress (OSS) is shown to significantly affect off-state breakdown behavior. This paper introduces a modified methodology for conducting OSS in scaled tri-gate devices at accelerated conditions that avoids artifacts associated with punch-through while enabling reliability risk assessment. The methodology is validated for both NMOS & PMOS devices and provides consistent degradation mechanism. Finally, it is shown that on-state gate-oxide TDDB remains the reliability limiter compared to OSS TDDB.

Degradation

10.1109/irps48227.2022.9764519

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Citations (2)

Microstructure Analysis of ALD Bi2Te3/Sb2Te3 Thermoelectric Nanolaminates

Meeting abstracts/Meeting abstracts (Electrochemical Society. CD-ROM) (2013)

Kai Zhang David Nminibapiel Madhavi Tangirala Venkata Sai Kiran Chakravadhanula Christian Kübel

Abstract not Available.

10.1149/ma2013-02/24/1866

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VO2 Films Prepared By Atomic Layer Deposition and RF Magnetron Sputtering

Meeting abstracts/Meeting abstracts (Electrochemical Society. CD-ROM) (2013)

Kai Zhang Madhavi Tangirala David Nminibapiel Venkateswara Pallem Christian Dussarrat

Abstract not Available.

Deposition

Cavity magnetron

10.1149/ma2013-02/24/1864

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A Reliability Overview of Intel’s 10+ Logic Technology

2022 IEEE International Reliability Physics Symposium (IRPS) (2020)

R. Grover Tony Acosta C. AnDyke Emre Armagan C. Auth

We provide a comprehensive overview of the reliability characteristics of Intel's 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel's FinFETs, seventh generation of strained silicon, fifth generation of high-k metal gate, multi-Vt options, contact over active gate, single-gate isolation, 14 metal layers, low-k inter-layer dielectric, multi-plate metal-insulator-metal capacitors, two thick-metal routing layers for low-resistance power routing, and lead-free packaging. The technology meets all relevant reliability metrics for certification.

10.1109/irps45951.2020.9128345

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Nanomechanical Properties of Atomic Layer Deposition Sb₂Te₃Thin Films

M. A. Mamun Dongdong Gu David Nminibapiel H. Baumeart Hans D. Robinson

Deposition

Layer by layer

10.1002/9781118357002.ch91

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Analysis of Resistive Switching Characteristics in Surface Anchored Metal Organic Framework (SURMOF) Films

Meeting abstracts/Meeting abstracts (Electrochemical Society. CD-ROM) (2015)

David Nminibapiel Pragya R. Shrestha Zhengbang Wang Kin P. Cheung Helmut Baumgart

In the quest for new nonvolatile memory devices many new device concepts and materials systems have emerged in recent years. Notably MRAMs, FeRAMs, STTRAMs and RRAMs have attracted considerable attention and research efforts. Particularly in RRAM, the majority of these new developments are focusing on inorganic materials systems and very little work has been reported on organic or hybrid organic-inorganic memory related materials systems. Here we report on the resistive switching characteristics of a class of hybrid designer solids HKUST-1(Hong Kong University of Technology1) (or [Cu 3 (BTC) 2 ]) SURMOF porous conductors which were loaded with ferrocene. SURMOF films are also referred to as porous coordination polymers (PCPs). The electrical conductivity of SURMOF films can be modulated by loading the pores with appropriate organic semiconductors. Loading with ferrocene or TCNQ can enable ion transport in addition to electron transport thus change the electrical conductivity. The SURMOF samples for this study have been grown on surface-functionalized Au-substrates by employing a layer-by-layer, liquid-phase epitaxial method. Device fabrication was carried out by depositing top electrodes from either Cu or Au using a commercial e-beam deposition system. Two different device stacks were fabricated and tested. The first device consisted of an Au/SURMOF/Cu/Au stack with SURMOF film thickness of around 75nm. The Cu/Au top electrode was deposited by e-beam evaporation with a thicknesses of 200nm and 25nm respectively and patterned with a shadow mask to produce disks of 200µm in diameter. The second device consisted of an Au/SURMOF/Al/Au stack with a SURMOF thickness of 10nm, 20nm and 50nm. The Al/Au top electrode was deposited by e-beam evaporation with a thicknesses of 700nm and 100nm respectively, and patterned with a shadow mask to yield disks of 150µm in diameter. A slow voltage ramp typically between -1.5V to +1.5V was used. Measurements have been performed on pristine samples directly after synthesis. Initially pristine SURMOF switching devices are in a high resistance state. In our device configuration the bottom electrode is grounded and the voltage is applied to the top electrode. In devices with Cu/Au as top electrode, ON was observed on negative voltage sweeps and OFF was observed on positive voltage sweeps. In devices with Al/Au top electrodes, ON was observed on positive voltage sweeps and OFF was observed on negative voltage sweeps. After increasing the voltage from 0 V to max. 0.75 V, a transition to a low resistance state is observed. The voltage was swept in the reverse polarity to switch from low to high resistance state. Current as high as 50mA was required to switch the device from low to high resistance state. Measurements were also performed on the unloaded SURMOF devices. Compared to the loaded device, the switching characteristics are quite poor. The observed phenomena are crucially dependent on ferrocene loading. Ferrocene loading increased the conductivity within the MOF layer and therefore lowers the resistance. The devices could be switched using pulse width longer than 20 ns. Although the device switched within tens of nanoseconds, the time of switching could not be established due to large device capacitance values. The polarity of the SET and RESET in the devices with the Cu as the top electrode rules out the possibility of Cu ion migration being the reason for formation and dissolution of the low resistance path during switching. Additionally, devices with Al top electrode were also measured. Similar to the Cu top electrode, the Al top electrode devices also showed resistive switching.

Resistive touchscreen

10.1149/ma2015-02/16/786

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A detailed comparison of various off-state breakdown methodologies for scaled Tri-gate technologies

2022 IEEE International Reliability Physics Symposium (IRPS) (2023)

K. Joshi David Nminibapiel M. Ghoneim D. Ali R. Ramamurthy

The source-drain punch-through current in off-state TDDB stress (OSS) is shown to significantly affect off-state breakdown behavior. This paper compares various OSS methodologies available in the literature and discusses how source-to-drain punch-through affects off-state breakdown and reliability. The proposed Drain-stress with Offset (DSO) OSS methodology limits punch-through to better reflect the actual field dependence of OSS breakdown for scaled tri-gate MOSFET technologies.

10.1109/irps48203.2023.10117954

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Atomic Layer Deposition of Antimony Telluride and Bismuth Telluride using (Me3Si)2Te with SbCl3 and Trimethylbismuth as Precursors

Meeting abstracts/Meeting abstracts (Electrochemical Society. CD-ROM) (2011)

Diefeng Gu David Nminibapiel Helmut Baumgart Hans D. Robinson Vladimir Kochergin

Abstract not Available.

Telluride

Bismuth telluride

Deposition

Bismuth

Cadmium telluride photovoltaics

10.1149/ma2011-02/26/1871

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Growth of Nanolaminates of Thermoelectric Bi₂Te₃/Sb₂Te₃by Atomic Layer Deposition

ECS Journal of Solid State Science and Technology (2014)

David Nminibapiel Kai Zhang Madhavi Tangirala Helmut Baumgart Venkata Sai Kiran Chakravadhanula

The fabrication of thermoelectric nanolaminate structures of alternating Bi2Te3 and Sb2Te3 ALD layers for thermoelectric application is reported. Trimethylsilyl telluride ((Me3Si)2Te), bismuth trichloride (BiCl3) and antimony trichloride (SbCl3) were utilized as chemical ALD precursors for telluride, bismuth and antimony, respectively. The results of field emission scanning electron microscopy (FE-SEM) indicate both metal tellurides exhibit the prevalent Volmer-Weber island growth mechanism with characteristic hexagonal crystallites. High resolution TEM X-section analysis reveals localized epitaxial growth of alternating ALD Bi2Te3 and Sb2Te3 layers within the large islands.

Bismuth

Bismuth telluride

Telluride

10.1149/2.014404jss

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Citations (13)