The co-packaging of optics and electronics provides a potential path forward to achieving beyond 50 Tbps top of rack switch packages. In a co-packaged design, the scaling of bandwidth, cost, and energy is governed by the number of optical transceivers (TxRx) per package as opposed to transistor shrink. Due to the large footprint of optical components relative to their electronic counterparts, the vertical stacking of optical TxRx chips in a co-packaged optics design will become a necessity. As a result, development of efficient, dense, and wide alignment tolerance chip-to-chip optical couplers will be an enabling technology for continued TxRx scaling. In this paper, we propose a novel scheme to vertically couple into standard 220 nm silicon on insulator waveguides from 220 nm silicon nitride on glass waveguides using overlapping, inverse double tapers. Simulation results using Lumerical's 3D Finite Difference Time Domain solver solver are presented, demonstrating insertion losses below -0.13 dB for an inter-chip spacing of 1 $μ$m, 1 dB vertical and lateral alignment tolerances of approximately $\pm$ 2.7 $μ$m, a greater than 300 nm 1 dB bandwidth, and 1 dB twist and tilt tolerance of approximately 2.3 degrees and 0.4 degrees, respectively. These results demonstrate the potential of our coupler for use in co-packaged designs requiring high performance, high density, CMOS compatible out of plane optical connections.
A novel ZnTe-on-Si waveguide system is presented and demonstrates a reduced TPA coefficient compared to pure silicon with a comparable nonlinear Kerr refractive index to achieve a significantly higher nonlinear FOM TPA for efficient nonlinear applications.
In this letter, we experimentally evaluate the effect of miniaturization and surface roughness on transmission losses within a Si/SiO2 waveguide system, and explain the results using a theoretical model. Micrometer/nanometer-sized waveguides are imperative for its potential use in dense integrated optics and optical interconnection for silicon integrated circuits. A theoretical model was employed to predict the relationship between the transmission losses of the dielectric silicon waveguide and its width. This model accurately predicts that loss increases as waveguide width decreases. Furthermore, we show that a major source of loss comes from sidewall roughness. We have constructed a complete contour map showing the interdependence of sidewall roughness and transmission loss, to assist users in their design of an optimal waveguide fabrication process that minimizes loss. Additionally, users can find an effective path to reduce the scattering loss from sidewall roughness. Using this map, we confirm that nanometer-size silicon waveguides with 0.1 dB/cm transmission loss are possible with the currently available technology.
0.6 dB coupling loss was observed for a lensed, asymmetric graded-index mode converter. The mode converter is used to couple light at 1550 nm from a single mode optical fiber to an on-chip waveguide with n=1.7
Amorphous silicon (a-Si), single-mode, channel waveguides were fabricated and measured with transmission losses as low as 6.5 dB/cm for the TE mode and 4.5 dB/cm for the TM mode. Variations in the PECVD a-Si deposition conditions yielded a-Si materials with bulk losses <1 dB/cm
Cavity-enhanced photosensitivity of As2S3 chalcogenide glass films is measured using planar micro-disk resonators. We observed infrared index trimming by 1550 nm wavelength light, cavity instability and confirmed the absence of two photon absorption.
Ge-on-Si p-i-n photodiodes with graded boron doping were grown and annealed at low temperatures. Annealing improved diode characteristics, with the highest performing diode annealed at 500°C for 3hr, Responsivity = 0.15 A/W and Jd = 170 µA/cm 2 at λ=1310nm, 0.5µm Ge, and no AR coating.
