Cryptographic circuits such as advanced encryption standard (AES) are vulnerable to correlation power analysis (CPA) side-channel attacks (SCAs), where an adversary monitors chip supply current signatures or electromagnetic (EM) emissions to decipher the value of embedded keys. This article describes an all-digital, fully synthesizable SCA-resistant 16-b serial AES-128 hardware accelerator fabricated in 14-nm CMOS, occupying 4900 μm 2 . Randomized byte-order shuffling through heterogeneous Sboxes, linear masked MixColumns, and dual-rail AddRoundKey circuits enable: 1) 9.2× lower correlation between current signatures and hamming distance (HD)/hamming weight (HW) power models compared to an unprotected AES implemented in 14-nm CMOS; 2) 2.3× attenuation of a correlation ratio for correct key guesses; 3) 839-Mb/s encryption throughput with 11-mW total power consumption measured at 750 mV, 25 °C; 4) peak energy efficiency of 390 Gbps/W measured at an energy optimal point of 290 mV, 25 °C, representing an overhead of 23% over the unprotected AES engine; 5) <; 1% performance impact compared to unprotected AES; 6) >1200× improvement in minimum-traces-to-disclosure (MTD) over an unprotected AES accelerator, with no successful CPA attacks observed after 12M encryptions; and 7) >1100× improvement in test vector leakage assessment (TVLA ) metric in power and EM time- and frequency-domain analyses.
In this work, we utilize electrically detected magnetic resonance via the bipolar amplification effect to explore the physical and chemical nature of defects at the 4H-SiC/SiO 2 interface in metal-oxide-semiconductor field effect transistors. Defects at and very near the 4H-SiC/SiO 2 interface are involved in bias temperature instabilities in 4H-SiC transistor technology. Of particular relevance to reliability physics, our results indicate that oxygen deficient silicon atoms in the near-interface oxide, known as E' centers, can be greatly reduced utilizing nitric oxide and barium annealing. E' centers have been directly linked to bias temperature instabilities in 4H-SiC technology.
SUMMARY An STM was built, in which the substrate is mounted on a piezoelectric bimorph. The compliance of the tip‐surface contact region is measured by modulating the vertical position of the tip and detecting the induced deflection of the bimorph. Tip‐surface compliances between 5 and 200 N/m were measured during STM operation. It is possible to use the compliance signal for operating the microscope's feedback loop. Stable feedback loop operation can be achieved for tip‐surface distances up to about 200 nm. By operating the microscope in this constant compliance mode, surfaces of arbitrary conductance can be imaged. For conductive surfaces the tunnelling current can be recorded simultaneously. On a Nb 3 Sn film conducting and isolating patches were detected using this method.
A 128-entry × 128b content addressable memory (CAM) design enables 145ps search operation in 1.0V, 32nm high-k metal-gate CMOS technology. A high-speed 16b wide dynamic AND match-line, combined with a fully static search-line and swapped XOR CAM cell simulations show a 49% reduction of search energy at iso-search delay of 145ps over an optimized high-performance conventional NOR-type CAM design, enabling 1.07fJ/bit/search operation. Scaling the supply voltage of the proposed CAM enables 0.3fJ/bit/search with 1.07ns search delay at 0.5V.
A 82,000μm 2 canonical Huffman encoder (CHE) for accelerating DEFLATE data compression is fabricated in 14nm CMOS. Concurrent 2-stage sorting and binary tree construction, opportunistic skipping of missing symbols during Huffman code generation, and in-line length-limitation without recursive weight pruning eliminates serial data dependency in encoder pipeline enabling 179Mcode/s throughout at 650MHz operation measured at 0.75V, 25°C with 1150cycle total CHE latency, 17× faster than previously reported hardware accelerators. Unified datapath for literal-length and distance symbol processing, optimal register-file partitioning, shared address generation and reconfigurable ALU circuits maximize logic sharing resulting in fully synthesizable 330Kgate design that improves area-efficiency by 25% over prior-art. Absence of custom memory macros enables robust ultra-low voltage operation down to 220mV with 36pJ/code peak energy-efficiency (4.9× higher than nominal) measured at near-threshold voltage operation of 290mV.
This paper describes a parity-checking fault-tolerant adder designed for 6.5 GHz operation with total power consumption of 54 mW, targeted for 65 nm 64-bit microprocessor execution cores. The adder is fully self-checking and guarantees 100% coverage of single-faults (including multi-bit output errors originating from single-faults) on any sequential/combinational node in the design. The sparse-tree design enables partial pre-computation of the critical carry-parities, resulting in 33% reduction in parity-computation delay overhead with a low 6% area overhead for fault-detection.
SiC MOSFETs show promise for high power and high temperature applications, but bias temperature instabilities may potentially limit the performance of these devices. Utilizing electrically detected magnetic resonance (EDMR), we show that three different defect centers are generated during NBTS. Although a complete understanding of the EDMR is not yet available, the results provide strong evidence for E' centers, hydrogen, and hydrogen complexes involvement in the NBTI phenomena.
Abstract Scanning force microscopy techniques were applied to investigate the surface of magnetic tapes and organic surfaces such as film forming and radiation‐sensitive polymeric materials. The unique potential of the method to derive quantitative data, that is, surface roughness and asymmetry parameters, is demonstrated. Force‐modulation experiments indicate that liquid/gas interfaces can be directly detected.
A relatively simple addition to many widely utilized semiconductor device characterization techniques can allow one to identify much of the atomic scale structure of point defects which play important roles in the electronic properties of the devices under study. This simple addition can also open up the possible exploration of the kinetics involved in some reliability phenomena as well as in multiple transport mechanisms. This addition is a small (0 to a few mT) time varying magnetic field centered upon zero field. A readily observable difference between various device responses at zero and small fields can be observed in a wide range of measurements often used in semiconductor device characterization. These measurements include metal-oxide-semiconductor field-effect transistor (MOSFET) charge pumping, metal-oxide-semiconductor (MOS) gated diode recombination current, so called direct current current-voltage (DCIV) measurements, deep level transient spectroscopy, and simple current measurements in dielectric films and in pn junctions. Multiple materials systems of great technological interest can be explored with the techniques. They are based on near zero field magnetoresistance (NZFMR) phenomena, spin-based quantum effects involving magnetic field induced changes which occur in multiple electronic transport phenomena. Because these spin-based changes are strongly affected by fundamentally well understood spin-spin interactions such as electron-nuclear hyperfine interactions or electron-electron dipolar interactions, this NZFMR response has quite substantial analytical power. The NZFMR techniques can be gainfully applied to device structures based upon numerous materials systems, among them being silicon dioxide, silicon, silicon carbide, silicon nitride and amorphous SiOC:H films utilized in interlayer dielectrics.
A 4×4 node systolic matrix-multiply accelerator with unified INT8/INTI6/FPI6 datapath and wide INT24/INT48/FP32 accumulators is fabricated in 14nm CMOS. Handshake-based routing circuits with multiple-node broadcast enable 8.8× higher energy-efficiency with 20% nonzero sparse matrices. INT8 mode reconfigures each node from lxl to 2×2 matrix multiplier for 2.9TOPS/W energy efficiency at 750mV, and up to 11.3TOPS/W at 280mV (near-threshold).
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