A 6.5GHz 54mW 64-bit Parity-Checking Adder for 65nm Fault-Tolerant Microprocessor Execution Cores
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This paper describes a parity-checking fault-tolerant adder designed for 6.5 GHz operation with total power consumption of 54 mW, targeted for 65 nm 64-bit microprocessor execution cores. The adder is fully self-checking and guarantees 100% coverage of single-faults (including multi-bit output errors originating from single-faults) on any sequential/combinational node in the design. The sparse-tree design enables partial pre-computation of the critical carry-parities, resulting in 33% reduction in parity-computation delay overhead with a low 6% area overhead for fault-detection.Keywords:
Microprocessor
Check pointing is the most popular fault tolerance method used in high-performance computing (HPC) systems. However, increasing failure rates requires more frequent checkpoints, thus makes check pointing more expensive. We present a checkpoint-free fault tolerance technique. It takes advantage of both data dependencies and communication-induced redundancies of parallel applications to tolerate fail-stop failures. Under the specified conditions, our technique introduces no additional overhead when there is no actual failure in the computation and recover the lost data with low overhead. We add fault-tolerant capacity to Newton's method by using our scheme and diskless check pointing. Numerical simulations indicate that our scheme introduces much less overhead than diskless check pointing does.
Software fault tolerance
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Consistent checkpointing provides transparent fault tolerance for long-running distributed applications. Performance measurements of an implementation of consistent checkpointing are described. The measurements show that consistent checkpointing performs remarkably well. Eight computation-intensive distributed applications were executed on a network of 16 diskless Sun-3/60 workstations, and the performance without checkpointing was compared to the performance with consistent checkpoints taken at two-minute intervals. For six of the eight applications, the running time increased by less than 1% as a result of the checkpointing. The highest overhead measured was 5.8%. Incremental checkpointing and copy-on write checkpointing were the most effective techniques in lowering the running time overhead. It is argued that these measurements show that consistent checkpointing is an efficient way to provide fault tolerance for long-running distributed applications.< >
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Increasing the reliability of a system always comes with a high price in performance/power/area overhead. Enabling error detection and correction features can be obtained by employing different kinds of redundancy including hardware, time, information, software or some combination of them. In many cases the imposed overhead is enormous. Fault tolerance is an important requirement for safety critical applications (e.g., automated driving), but significant power/area overhead is not acceptable. This paper summarizes several strategies and methods how to reduce the introduced overhead, while still providing a respectable level of fault tolerance features. Two main methodologies are discussed: static and dynamic. Static methods address the overhead by performing a static trade-off between the achieved level of fault tolerance and the introduced overhead. Dynamic methods on the other hand are based on the actual application requirement, and are dynamically varying the required overhead to fulfill the safety requirements of the application. This paper summarizes practical examples and results in this field.
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Adder is a circuit that is combinational andcalculates the sum of three (full adder) or two (half adder) inputs. Full adder can be cascaded to produce n-stages of adder. This cascaded adder structure is called as parallel adder. The sum and carry outputs of any stage cannot be calculated until the input carry occurs, this leads to a delay in the addition process. In order to overcome the delay, carry look ahead adder is proposed which is said to be a fast adder. To improve the speed of vary look ahead adder, Spurious Power Suppression Technique (SPST) is used. This paper discusses 8-bit adder consisting of three architectures parallel adder, normal carry look ahead adder and SPST carry look ahead adder. The results were simulated using Xilinx tools and as shown, the power has decreased for both the SPST carry look ahead adder and the SPST ripple carry adder. The code was written in Verilog HDL and tested on a Xilinx FPGA test board as a part of a velocity measurement circuit for an Electromagnetic Projectile Launcher.Keywords: Adder, Full Adder, Power, Parallel Adder, SPST
Carry-save adder
Serial binary adder
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Power consumption and speed have been well determined with the help of arithmetic module, adder. So the need of high speed, error tolerance and power efficiency nature of few applications have been improved the development of approximate adders. To increase the effectiveness of integrated circuits, utilizing the tradeoff between accuracy and cost of hardware has a great potential. Various approximate adders have been proposed using this technique. By using systematic methodology, optimizing the architecture for approximate adders have been implemented. The adder is called optimized lower part constant-OR adder (LOCA). The adder has been proposed by redesigning its logic circuit.
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The paper describes performance measurements of an implementation of independent checkpointing in a network of workstations. Independent checkpointing is a simple technique for providing fault tolerance in distributed systems. Because processes do not coordinate during checkpointing, this technique has a low run-time overhead. To avoid the classical domino effect, our implementation relies on a message logging mechanism. We have measured fault management overhead for different kinds of parallel applications. The costs of checkpointing are very low. However, message logging introduces a sizeable overhead. We compare these results to other works implementing different checkpointing policies, and we show that independent checkpointing is an efficient way to provide fault tolerance for long-running distributed applications composed of processes exchanging small streams of data.< >
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In a digital circuit, the addition of certain number of bits is generic operation used in order to pare the complexity of the circuit and it operation. The selection of proper adder with requisite properties is more important for the efficient working of the circuit. Comparisons among different adders have been performed, which helps to reduce the laborious work. Adders that have been compared are all of 4 bit and have been synthesized using Xilinx synthesis tool and simulated using the Xilinx simulation tool. The outcomes of synthesis reports and simulation of the circuit helps in finding out the different properties. For paradigm, the area consumed or the number of slices taken up by the circuit and speed can be calculated. These properties make out the difference in the operation and performances of the adders. The adders that have been compared in this paper are Ripple Carry Adder, Carry Look Ahead Adder, Carry Save adder, Carry Skip Adder, Carry select adder, Modified Carry Select Adder and Kogge Stone Adder based on two basic aspects namely, number of slices i.e., area occupied and speed.
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This paper proposes a new approximate adder that increases the accuracy of addition while ensuring acceptable hardware performance. The proposed adder implemented with a 32-nm CMOS technology reduces the area, power, and delay by 40%, 43%, and 50% of those of the traditional accurate adder, respectively. Moreover, the proposed adder shows a better tradeoff performance than the existing approximate adders considered in this paper when jointly evaluating both accuracy and hardware performance. Specifically, the proposed adder enhances power-mean relative error distance (MRED) product, energy-MRED product, and area-MRED product by up to 65%, 65%, and 64% compared to the approximate adder considered herein.
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In this paper, efficient design of approximate adders to effective utilization of the FPGA resources are proposed. The designs are proposed to analyze the differences between power, area and delay in the adders. The following are the approximate adders such as low error and area efficient approximate adder (LEADx), area and power efficient approximate adder (APEx) and high speed and power efficient approximate adder (HSPEx). This type of adders consists of two parts where the least significant part represents approximate adder and most significant part represents accurate adder. The purpose of the approximate adder is to lessen the power, area and delay in the adders. LEADx and APEx has more delay compared to HSPEx approximate adder. HSPEx significantly reduces more area compared to APEx and APEx reduces more area compared to LEADx approximate adder. The HSPEx approximate adder uses the inner stage input-output pipelining technique to reduce the use of LUTs and increase the speed of the adder whereas APEx adder uses truncation technique by fixing constant 1 to some of bits in the adder. Compared to other approximate adders the HSPEx adder absorbs relatively less power. The synthetization and simulation of the proposed method is performed using Xilinx VIVADO.
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