Chemical-mechanical polishing (CMP) is an enabling technique used in deep-submicrometer VLSI manufacturing to achieve long range oxide planarization. Post-CMP oxide topography is highly related to local pattern density in the layout. To change local pattern density and, thus, ensure post-CMP planarization, dummy features are placed in the layout. Based on models that accurately describe the relation between local pattern density and post-CMP planarization by Stine et al. (1997), Ouma et al. (1998), and Yu et al. (1999), a two-step procedure of global density assignment followed by local insertion is proposed to solve the dummy feature placement problem in the fixed-dissection regime with both single-layer and multiple-layer considerations. Two experiments conducted with real design layouts gave excellent results by reducing simulated post-CMP topography variation from 767 /spl Aring/ to 152 /spl Aring/ in the single-layer formulation and by avoiding cumulative effect in the multiple-layer formulation. The simulation result from single-layer formulation compares very favorably both to the rule-based approach widely used in industry and to the algorithm by Kahng et al (1999). The multiple-layer formulation has no previously published work.
The authors present two algorithms to optimally select implementations for rectangular and L-shaped subfloorplans. The algorithms are designed specifically for the floorplan optimization algorithm given by T.-C. Wang and D.F. Wong (see Proc. 27th ACM/IEEE Des. Autom. Conf., p.180-6 (1990)), but they can also be applied to other algorithms as well. The experimental results, based on incorporating the two algorithms into Wang's algorithm, whose performance was considerably improved were very encouraging. For the test runs where Wang's algorithm failed to run, the algorithms helped to produce satisfactory solutions. >
Article Free Access Share on Delay minimal decomposition of multiplexers in technology mapping Authors: Shashidhar Thakur Synopsys Inc., 700 E. Middlefield Road, Mountainview, CA Synopsys Inc., 700 E. Middlefield Road, Mountainview, CAView Profile , D. F. Wong Department of Computer Sciences, University of Texas at Austin, Austin, TX Department of Computer Sciences, University of Texas at Austin, Austin, TXView Profile , Shankar Krishnamoorthy Synopsys Inc., 700 E. Middlefield Road, Mountainview, CA Synopsys Inc., 700 E. Middlefield Road, Mountainview, CAView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 254–257https://doi.org/10.1145/240518.240565Online:01 June 1996Publication History 5citation216DownloadsMetricsTotal Citations5Total Downloads216Last 12 Months3Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF
In the pursuit of alternatives to traditional optical lithography, block copolymer directed self-assembly (DSA) has emerged as a low-cost, high-throughput option. However, issues of defectivity have hampered DSA's viability for large-scale patterning. Recent studies have shown copolymer fill level to be a crucial factor in defectivity, as template overfill can result in malformed DSA structures and poor LCDU after etching. For this reason, it is previously demonstrated the use of sub-DSA resolution assist features (SDRAFs) as a method of evening out template density. In this work, we propose an algorithm to place SDRAFs in random logic contact/via layouts. By adopting this SDRAF placement scheme, we can significantly improve the density unevenness and the resources used are also optimized. This is the first work to investigate the placement of SDRAFs in order to mitigate the DSA density variation problem, and it can be adopted for the mass deployment of DSA.
In this paper, we give a method to design FPGA logic modules, based on an extension of classical work on designing Universal Logic Modules (ULM). Specifically, we give a technique to design a class of logic modules that specialize to a large number of functions under complementations and permutations of inputs, bridging of inputs and assignment of 0/1 to inputs. Thus, a lot of functions can be implemented using a single logic module. The significance of our work lies in our ability to generate a large set of such logic modules. A choice can be made from this set based on design criteria. We demonstrate the technique by generating a set of 471 8-input functions that have a much higher coverage than the 8-input cells employed by Actel's FPGAs. Our functions can specialize to up to 23 times the number of functions that Actel functions can. We also show that by carefully optimizing these functions one can obtain multi-level implementations of them that have delays within 10% of the delays of Actel modules. We demonstrate the effectiveness of these modules in mapping benchmark circuits. We observed a 16% reduction in area and a 21% reduction in delay using our logic modules instead of Actel's on these circuits.
Maze routing is usually the most time-consuming step in global routing or detailed routing. One possible way to accelerate it is to use parallel computing. Net-level parallelism is commonly used but it is affected greatly by the dependency between nets. There are few GPU-friendly parallel maze routers, which can be nontrivial to design. In this paper, we propose a pathfinding-level parallel 3D routing scheme. We implemented it in CUDA and applied it to the coarsened maze routing stage of an open source global router CUGR. Compared with CUGR on the ICCAD 2019 global routing contest benchmark suite, we achieve an average of 16 x speedup in the coarsened maze routing stage without loss of quality.
In this paper we present Cpp-Taskflow, a C++ parallel programming library that enables users to quickly develop parallel applications using the task dependency graph model. Developers formulate their application as a task dependency graph and Cpp-Taskflow will manage the task execution and concurrency control.The task graph model is expressive and composable. It can express both regular and irregular parallel patterns, and developers can quickly compose large programs from small parallel modules. Cpp-Taskflow has an intuitive and unified API set. Users only need to learn the APIs to build and dispatch a task graph and no complex parallel programming concept is required. We have conducted experiments using both micro-benchmarks and real-world applications and Cpp-Taskflow outperforms state-of-the-art parallel programming libraries in both runtime and coding effort. Cpp-Taskflow is open-source and has been used in both industry and academic projects. From our users' feedback, we believe Cpp-Taskflow can benefit the industry and research community greatly through its ease-of-programming and inspire new research directions in multimedia system/software design.
Article Free Access Share on Fast evaluation of sequence pair in block placement by longest common subsequence computation Authors: Xiaoping Tang Department of Computer Sciences, University of Texas at Austin Department of Computer Sciences, University of Texas at AustinView Profile , Ruiqi Tian Department of Computer Sciences, University of Texas at Austin and Motorola Computational Technology Lab, Austin, Texas Department of Computer Sciences, University of Texas at Austin and Motorola Computational Technology Lab, Austin, TexasView Profile , D. F. Wong Motorola Computational Technology Lab, Austin, Texas Motorola Computational Technology Lab, Austin, TexasView Profile Authors Info & Claims DATE '00: Proceedings of the conference on Design, automation and test in EuropeJanuary 2000 Pages 106–111https://doi.org/10.1145/343647.343713Online:01 January 2000Publication History 62citation483DownloadsMetricsTotal Citations62Total Downloads483Last 12 Months15Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF
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