Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
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Abstract:
Chemical-mechanical polishing (CMP) is an enabling technique used in deep-submicrometer VLSI manufacturing to achieve long range oxide planarization. Post-CMP oxide topography is highly related to local pattern density in the layout. To change local pattern density and, thus, ensure post-CMP planarization, dummy features are placed in the layout. Based on models that accurately describe the relation between local pattern density and post-CMP planarization by Stine et al. (1997), Ouma et al. (1998), and Yu et al. (1999), a two-step procedure of global density assignment followed by local insertion is proposed to solve the dummy feature placement problem in the fixed-dissection regime with both single-layer and multiple-layer considerations. Two experiments conducted with real design layouts gave excellent results by reducing simulated post-CMP topography variation from 767 /spl Aring/ to 152 /spl Aring/ in the single-layer formulation and by avoiding cumulative effect in the multiple-layer formulation. The simulation result from single-layer formulation compares very favorably both to the rule-based approach widely used in industry and to the algorithm by Kahng et al (1999). The multiple-layer formulation has no previously published work.Keywords:
Chemical Mechanical Planarization
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【As device sizes are scaled down to submicron dimensions, planarization technology becomes increasingly important for both device fabrication and formation of multilevel interconnects. Chemical mechanical polishing (CMP) has emerged recently as a new processing technique for achieving a high degree of planarization for submicron VLSI applications. The polishing process has many variables, and most of which are not well understood. The factors determine the planarization performance are slurry and pad type, insert material, conditioning technique, and choice of polishing tool. Circuit density, pattern size, and wiring layout also affect the performance of a CMP planarization process. This paper presents the results of studies on CMP process window characterization for 0.35 micron process with 5 metal layers.】
Chemical Mechanical Planarization
Process window
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Chemical and mechanical properties of a surface reaction layer are essential to improve planarization in Cu-CMP. We compared the reaction layers on Cu surfaces formed by dipping in APS and H2O2 slurries and show that a thinner, mechanically stronger, and corrosion-resistant layer is preferable. It enables preferential polishing of the convex surfaces and consequently relaxes dishing after Cu-CMP. Controlling Cu oxidation reaction to form Cu2O in the slurry is essential for achieving further improvements of the planarization.
Chemical Mechanical Planarization
Nanometre
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Chemical mechanical planarization (CMP) of copper dual Damascene is described. Dishing of the copper layer can be controlled by the CMP employing non-abrasive MnO/sub 2/ slurry. Removal rate ratio of the Cu/barrier layer can be reduced from 2.8 to unity with doping of antioxide additive in the slurry. Dishing still appears at the rate of 2.8 and dishing free CMP can be attained at unit. Scratches are formed in this CMP.
Chemical Mechanical Planarization
Copper interconnect
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The chemical-mechanical global planarization mechanism to the common low-k dielectric material is analyzed.The effect of several factors including pressure,abrasive,pH and temperature in the chemical-mechanical polishing process of low-k dielectric material on the polishing rate and surface appearance are discussed.
Chemical Mechanical Planarization
Low-k dielectric
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Chemical mechanical planarization (CMP) has been used to fabricate a 0.35 micrometers 16 Meg SRAM with quadruple polysilicon stacks. The use of CMP results in complete planarization of over one micron of topography. CMP planarization results in improved photolithography depth of field when compared to standard resist etchback planarization (REB). Data from a lot processed using CMP at contact dielectric and interlayer dielectric is compared to a lot that was processed using standard REB for planarization.
Chemical Mechanical Planarization
Megabit
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Chemical-mechanical polishing(Chemical Mechanical Polishing,CMP)is currently only able to provide the global planarization technology,its mechanism of polishing is currently the most popular. A survey of some models was given which consider the polishing properties of polishing liquid and polishin pads,and the relevant characteristics of each model was analyzed,at last the development and research directions of the CMP model was prospected.
Chemical Mechanical Planarization
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Chemical Mechanical Planarization
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An interlayer dielectric process for GaAs is demonstrated in this paper. The interlayer dielectric process uses CMP for planarization of a PECVD dielectric. This paper explains GaAs CMP processing and the advantages of using a planarized PECVD interlayer dielectric.
Chemical Mechanical Planarization
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A macromodel for changes in a pad surface by dressing and polishing is proposed. A polishing pad is divided into small areas and it is assumed that each area takes an “H” (= high) or “L” (= low) condition. The condition is changed by dressing or polishing, and the total chemical mechanical planarization (CMP) performance is determined by the average pad condition. The results from equations are compared with experimental data, and good correspondence is confirmed. Various CMP behaviors are well explained by the equations, such as polishing rate stabilization by dummy running, the differences in the stability time and polishing rate between in situ dressing and ex situ dressing, and polishing rate behaviors for patterned wafers. This new model can be used to predict process performances, to optimize process conditions, or to indicate the direction of consumable development.
Chemical Mechanical Planarization
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Multilevel metallization is a key process for the technology generations below 0.5μm. As the design rules are going smaller, the limits of the classical SOG Etch-Back process are reached in terms of process complexity and long distance planarization. The solution to this problem is to use a Chemical Mechanical Polishing technique for the dielectric planarization. In this paper, we will demonstrate that this CMP technique is compatible with a 0.35 CMOS technology in terms of transistor behaviour and triple metal process assembly.
Chemical Mechanical Planarization
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