Among the technological developments pushed by the adoption of Through Silicon Vias and 3D Stacked IC technologies, wafer thinning on a temporary carrier has become a critical element in device processing over the past years. First generation of adhesive materials enabled the integration of the first devices at the expense of capping the thermal budget. Hence new generation materials are being explored to overcome this limitation and further bring the process complexity down.
As the need for higher degrees of function integration on chips continues to rise, chip-to-chip connection density exponentially increases. The continuous push for denser interconnects has brought conventional FO-WLP to its limit. A novel FO-WLP concept has been proposed to enable 20-μm pitch interconnect chip-to-chip. To achieve this density and to further scale it down, a critical element is ultra-precise die-to-die positioning in the micron range. Advances in temporary bonding materials and carrier systems are required to enable such applications.
Extreme thinned wafer transfer technologies have been demonstrated by combining a selected set of temporary and permanent bonding materials. The extreme thinning was performed on the backside of a top wafer bonded on carrier wafer with the temporary glue material, subsequently followed by grinding, polishing and plasma dry etching to a final thickness of 5 μm. The properties of the temporary adhesive have been selected to be compatible with a permanent thermocompression bond of the extreme thin wafer to a final target substrate. Thus, the high thermal deformation resistance of the temporary adhesive is key. As we are dealing with extremely thin substrate, the required process uniformity and total thickness variation of each material are crucial. Hence after the spin-coating, the permanent bond polymer was planarized by a surface planer process. The performance benefit brought by this process and the final transfer steps will also be discussed.
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