Abstract Ferroelectric SiBi2Ta2O9 capacitors with Pt electrodes were measured to have a non-volatile polarization of 6.6 μC/cm2 using 3 V pulse polarization measurements, a leakage current of less than 3×10−9 A/cm2 at 3 V, and a breakdown of voltage greater than 20 V. The temperature dependence of hysteresis loops were measured to 200 °C and both the non-volatile polarization and coercive field were observed to decrease with temperature. Process damage caused by CVD of overlying dielectrics and contact window plasma etching was reversed by oxygen annealing. Good resistance against both fatigue and imprint were observed.
Experimental data and simulation results for submicron MOSFETs are reported and used to support a physical explanation for two important anomalies in the dependence of device threshold voltage on channel length. They are the widely observed increase in threshold voltage with decreasing channel length (roll-up), and the more recent observation that the ultimate threshold voltage decrease (roll-off) occurs at a rate which is far in excess of that which can be explained with conventional models of laterally uniform channel doping. A model that attributes roll-up as well as roll-off to lateral redistribution of doping near the source and drain junctions is proposed. This lateral redistribution is caused by crystal defects formed during post-source/drain-implant anneal. The resulting profile consists of an enhancement of background doping adjacent to the junction edge, bounded by a depression of the doping farther into the channel.< >
In this paper, a 0.25 mum CMOS technology using trench gate structure is developed, and excellent short channel effect and device characteristics are obtained. Furthermore, the entire structure is fully planarized with shallow trench isolation (STI) [2]. and buried trench gate in both silicon substrate and STi regions. Because it is fully planarized, the structure is also highly suitable for further planarized multi-level metal interconnection approaches.
Vertical p-channel MOSFETs have been experimentally fabricated and characterized. Device characteristics of vertical p-channel MOSFETs are comparable to those of planar surface devices. Conduction current of a vertical transistor can be increased as much as four times that of a planar transistor for the same device area. The feature of large W/L ratio allows further increase in device density. Conduction current increases linearly with the channel width. No 3D current conduction degradation effect has been observed. It is found that the crystallographic orientation of the conduction channel has some effect on the threshold and sub-threshold characteristics, due to oxide thickness difference or fixed charges in the oxide interface.< >
In this paper we report on an exploratory metal oxide semiconductor field effect transistor (MOSFET) device which we are currently investigating which requires 100 nm lithography at all critical levels to achieve a completely fully scaled 100 nm device structure. The device also incorporates a novel trench isolation scheme whereby the isolation trenches are etched after the gate electrodes have been formed leading to a butted gate configuration. The device further incorporates fully overlapped contacts to the gate, source, and drain regions in order to provide maximum contact area. We believe that this structure will provide a good basis for exploring the density and performance limits of 100 nm-scale devices. We describe here the structure of the proposed device and then we propose a suitable method of fabrication. This is followed by a demonstration of suitable nanofabrication techniques which are based, in each case, on high resolution electron beam lithography and precision reactive ion etching. Finally, we assess the feasibility of integrating these techniques in order to realize the proposed device.
