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D. Linten

6

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Si,GeおよびIII/Vチャネルを用いたFinFETとGAA北西部における自己加熱【Powered by NICT】

2016
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SOFT ERRORS AND NBTI IN SiGe pMOS TRANSISTORS D. M FleetwoodJ*, E. X ZhangJ, G. X DuanJ, C. X ZhangJ, 1. K. SamselJ, N. C. HootenJ,

2014
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ofthetransistor, heavily attenuating thepossible residual voltage overshoot attheinput fortheESDfrequency range, Integrated designs indeep-submicron CMOS require ESD andthusincreasing theprotection level. protection fortheir I/Opins. Since CMOS scaling drastically

2007
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Impact of scaling on analog/RF CMOS performance

2004 SSICT | International Conference on Solid-State and Integrated Circuits Technology
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Citations (15)