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Yusuke Okaniwa
Yusuke Okaniwa
Keio University
Computer science
Electronic engineering
CMOS
Electrical engineering
Comparator
4
Papers
75
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A 40–44 Gb/s 3 $\times$ Oversampling CMOS CDR/1:16 DEMUX
2007
ISSCC | International Solid-State Circuits Conference
Nikola Nedovic
Nestoras Tzartzanis
Hirotaka Tamura
Francis M. Rotella
Magnus O. Wiklund
Yuma Mizutani
Yusuke Okaniwa
Tadahiro Kuroda
Junji Ogawa
William W. Walker
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Citations (20)
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique
2005
IEEE Journal of Solid-state Circuits
Yusuke Okaniwa
Hirotaka Tamura
Masaya Kibune
Daisuke Yamazaki
Tsz-shing Cheung
Junji Ogawa
Nestoras Tzartzanis
William W. Walker
Tadahiro Kuroda
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Citations (47)
SESSION 13 Multi Gb/s Serial Receivers
2004
Symposium on VLSI Circuits
Tapa I
A. Amerasekera
C. Kim
A. Iwata
Yusuke Okaniwa
Hirotaka Tamura
Masaya Kibune
Daisuke Yamazaki
Tsz-shing Cheung
Junji Ogawa
Nestoras Tzartzanis
Tadahiro Kuroda
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A 0.11 /spl mu/m CMOS clocked comparator for high-speed serial communications
2004
VLSIC | Symposium on VLSI Circuits
Yusuke Okaniwa
Hirotaka Tamura
Masaya Kibune
Daisuke Yamazaki
Tsz-shing Cheung
Junji Ogawa
Nestoras Tzartzanis
William W. Walker
Tadahiro Kuroda
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Citations (8)
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