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Masaru Osada
Masaru Osada
University of Tokyo
Computer science
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Electronic engineering
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A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with −80-dBc Reference Spur
2021
VLSIC | Symposium on VLSI Circuits
Zule Xu
Masaru Osada
Tetsuya Iizuka
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