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Rundong Jia

Peking University

17

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402

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Si/SnS2 Vertical Heterojunction Tunneling Transistor with Ionic-Liquid Gate for Ultra-Low Power Application

2021 CSTIC | China Semiconductor Technology International Conference
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Vertical SnS2/Si heterostructure for tunnel diodes

2020 Science in China Series F: Information Sciences
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Complementary tunneling transistors based on WSe2/SnS2 van der Waals heterostructure

2020 Science in China Series F: Information Sciences
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Dual-Gated MoS2 Neuristor for Neuromorphic Computing

2019 ACS Applied Materials & Interfaces
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Vertical WS 2 /SnS 2 van der Waals Heterostructure for Tunneling Transistors

2018 Scientific Reports
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New Insights Into Energy Efficiency of Tunnel FET With Awareness of Source Doping Gradient Variation

2018 IEEE Transactions on Electron Devices
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Corrections to “A Novel Tunnel FET Design Through Adaptive Bandgap Engineering With Constant Sub-Threshold Slope Over 5 Decades of Current and High ${I_{{\mathrm {ON}}}}/{I_{{\mathrm {OFF}}}}$ Ratio”

2018 IEEE Electron Device Letters
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Neuromorphic Computing: Ion Gated Synaptic Transistors Based on 2D van der Waals Crystals with Tunable Diffusive Dynamics (Adv. Mater. 21/2018)

2018 Advanced Materials
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Ion Gated Synaptic Transistors Based on 2D van der Waals Crystals with Tunable Diffusive Dynamics

2018 Advanced Materials
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Design and Simulation of a Novel Graded-Channel Heterojunction Tunnel FET With High ${I} _{\scriptscriptstyle\text {ON}}/{I} _{\scriptscriptstyle\text {OFF}}$ Ratio and Steep Swing

2017 IEEE Electron Device Letters
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