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Hao Jan Chao
Hao Jan Chao
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Electronic engineering
Computer science
Synchronization
Real-time computing
2
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9
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Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains
2010
DFT | Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Shianling Wu
Laung-Terng Wang
Lizhen Yu
Hiroshi Furukawa
Xiaoqing Wen
Wen-Ben Jone
Nur A. Touba
Feifei Zhao
Jinsong Liu
Hao Jan Chao
Fangfang Li
Zhigang Jiang
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Citations (8)
Practical Challenges in Logic BIST Implementation Case Studies
2008
ATS | Asian Test Symposium
Shianling Wu
Hiroshi Furukawa
Boryau Sheu
Laung-Terng Wang
Hao Jan Chao
Lizhen Yu
Xiaoqing Wen
Michio Murakami
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Citations (1)
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