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Kazutoyo Takano
Kazutoyo Takano
Melco
Electrical engineering
Electronic engineering
Voltage
Annealing (metallurgy)
Engineering
3
Papers
19
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Analysis of a drain-voltage oscillation of MOSFET under high dV/dt UIS condition
2012
ISPSD | International Symposium on Power Semiconductor Devices and IC's
Shinya Soneda
Atsushi Narazaki
Tetsuo Takahashi
Kazutoyo Takano
Shigenori Kido
Yusuke Fukada
Kensuke Taguchi
Tomohide Terashima
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A marvelous low on-resistance 20V rated self alignment trench MOSFET (SAT-MOS) in a 0.35μm LSI design rule with both high forward blocking voltage yield and large current capability
2004
ISPSD | International Symposium on Power Semiconductor Devices and IC's
A. Narazaki
Kazutoyo Takano
K. Oku
H. Hamachi
Tadaharu Minato
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Citations (1)
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