Old Web
English
Sign In
Acemap
>
authorDetail
>
J. Radecker
J. Radecker
Qimonda
Electronic engineering
Dram
AND gate
Electrical engineering
MOSFET
3
Papers
40
Citations
0.00
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (3)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
6F 2 buried wordline DRAM cell for 40nm and beyond
2008
IEDM | International Electron Devices Meeting
Till Schloesser
Frank Jakubowski
J. v. Kluge
Andrew Graham
Stefan Slesazeck
Martin Popp
Peter Baars
Klaus Muemmler
Peter Moll
K. Wilson
Axel Buerke
Daniel Koehler
J. Radecker
E. Erben
U. Zimmermann
T. Vorrath
B. Fischer
G. Aichmayr
R. Agaiby
W. Pamler
Thomas Schuster
W. Bergner
Wolfgang Mueller
Show All
Source
Cite
Save
Citations (36)
Reduction of layout variations with stress-compensated hybrid STI fills: a comprehensive analysis
2008
VLSI-TSA | International Symposium on VLSI Technology, Systems, and Applications
M. Stadele
G. Ilicali
Erhard Landgraf
Matthias Goldbach
S. Finsterbusch
J. Lindolf
J. Radecker
B. Uhlig
Show All
Source
Cite
Save
Citations (1)
Selective Oxide (SelOx) Deposition as Unique Gap-Fill Solution for Shallow Trench Isolation
2007
ASMC | Advanced Semiconductor Manufacturing Conference
H. M. Lindemann
J. Radecker
H.-P. Sperlich
Show All
Source
Cite
Save
Citations (3)
1