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Andrew Leaver
Andrew Leaver
Altera
Programmable logic device
Computer science
Parallel computing
Real-time computing
Field-programmable gate array
5
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66
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Adaptive delay estimation for partitioning-driven PLD placement
2003
IEEE Transactions on Very Large Scale Integration Systems
Michael D. Hutton
Khosrow Adibsamii
Andrew Leaver
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Citations (12)
Timing-driven placement for hierarchical programmable logic devices
2001
FPGA | Field Programmable Gate Arrays
Michael D. Hutton
Khosrow Adibsamii
Andrew Leaver
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Citations (21)
Programmable memory blocks supporting content-addressable memory
2000
FPGA | Field Programmable Gate Arrays
Frank Heile
Andrew Leaver
Kerry Veenstra
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Joining and beginning / output medium circuits for programmable logic integrated
2000
Wei-Jen San Jose Huang
Michael San Jose Hutton
Peter Kazarian
Andrew Leaver
Victor San Jose Maruri
David W. Mendel
Tony San Jose Ngai
Jim Park
Rakesh San Jose Patel
Bruce San Jose Pederson
James Schleicher
Sergey San Jose Shumarayev
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Hybrid product term and LUT based architectures using embedded memory blocks
1999
FPGA | Field Programmable Gate Arrays
Frank Heile
Andrew Leaver
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Citations (26)
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