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Takuro Amashita

Kobe University

6

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54

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NMOS-inside 6T SRAM layout reducing neutron-induced multiple cell upsets

2012 IRPS | International Reliability Physics Symposium
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Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure

2011 IOLTS | International On-Line Testing Symposium
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Bit error and soft error hardenable 7T/14T SRAM with 150-nm FD-SOI process

2011 IRPS | International Reliability Physics Symposium
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