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Chung-Jung Wu
Chung-Jung Wu
Industrial Technology Research Institute
Through-silicon via
Strain energy release rate
Electronic engineering
Delamination
Miniaturization
3
Papers
25
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Energy Release Rate Estimation for Through Silicon Vias in 3-D IC Integration
2014
IEEE Transactions on Components, Packaging and Manufacturing Technology
Ming-Che Hsieh
Sheng-Tsai Wu
Chung-Jung Wu
John H. Lau
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Citations (10)
Energy release rate investigation for through silicon vias (TSVs) in 3D IC integration
2011
EuroSimE | International Conference on Thermal, Mechanial and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems
Ming-Che Hsieh
Sheng-Tsai Wu
Chung-Jung Wu
John H. Lau
Ra-Min Tain
Wei-Chung Lo
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Citations (14)
Impact of Slurry in Cu CMP (Chemical Mechanical Polishing) on Cu Topography of Through Silicon Vias (TSVs), Re-distribution Layers, and Cu Exposure
2011
Electronic Components and Technology Conference
Jenny Chen
Pei-Jer Tzeng
Shang-Wei Chen
Chung-Jung Wu
Chien-Chou Chen
Yu-Chen Hsin
John H. Lau
Yi-Feng Hsu
Shen Hong Shen
Shu-chuan Liao
Chi-Hon Ho
Curry Lin
Tzu-Kun Ku
Ming-chih J. Kao
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