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K. Park
K. Park
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Integrated circuit layout
Parametric statistics
Logic synthesis
Optical proximity correction
Design flow
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Design rule optimization for 65-nm-node (CMOS5) BEOL using process and layout decomposition methodology
2004
K. Honda
K. Peter
Y. Zhang
B. Yu
K. Park
Xiaolei Li
K. Michaels
Shinichi Yamada
T. Noguchi
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