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Hirokazu Yonezawa

Panasonic

5

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Gate-level aged timing simulation methodology for hot-carrier reliability assurance

2000 DAC | Design Automation Conference
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Gate-level aged timing simulation methodology for hot-carrier reliability assurance

2000 ASP-DAC | Asia and South Pacific Design Automation Conference
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Ratio based hot-carrier degradation modeling for aged timing simulation of millions of transistors digital circuits

1998 IEDM | International Electron Devices Meeting
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