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Hirokazu Yonezawa
Hirokazu Yonezawa
Panasonic
Electronic engineering
Computer science
Very-large-scale integration
Clock skew
Slew rate
5
Papers
39
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A Modeling Methodology and Body Effect Analysis for Hot-Carrier Reliability Simulation of Logic Circuits
2002
IEICE Transactions on Electronics
Norio Koike
Hirokazu Yonezawa
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Gate-level aged timing simulation methodology for hot-carrier reliability assurance
2000
DAC | Design Automation Conference
Yoshiyuki Kawakami
Jingkun Fang
Hirokazu Yonezawa
Nobufusa Iwanishi
Lifeng Wu
A. I-Hsien Chen
Norio Koike
Ping Chen
Chune-Sin Yeh
Zhihong Liu
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Gate-level aged timing simulation methodology for hot-carrier reliability assurance
2000
ASP-DAC | Asia and South Pacific Design Automation Conference
Yoshiyuki Kawakami
Jingkun Fang
Hirokazu Yonezawa
Nobufusa Iwanishi
Lifeng Wu
Alvin I-Hsien Chen
Norio Koike
Ping Chen
Chune-Sin Yeh
Zhihong Liu
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Citations (2)
GLACIER: a hot carrier gate level circuit characterization and simulation system for VLSI design
2000
ISQED | International Symposium on Quality Electronic Design
Lifeng Wu
Jingkun Fang
Hirokazu Yonezawa
Yoshiyuki Kawakami
Nobufusa Iwanishi
Heting Yan
Ping Chen
Alvin I-Hsien Chen
Norio Koike
Yoshifumi Okamoto
Chune-Sin Yeh
Zhihong Liu
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Citations (21)
Ratio based hot-carrier degradation modeling for aged timing simulation of millions of transistors digital circuits
1998
IEDM | International Electron Devices Meeting
Hirokazu Yonezawa
Jingjun Fang
Yoshiyuki Kawakami
Nobufusa Iwanishi
Lifeng Wu
Alvin I. Chen
Norio Koike
Chune-Sin Yeh
Zhihong Liu
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Citations (15)
1