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David Nguyen

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RDRAM/spl reg/ channel design with 32-bit 4.8 GB/s memory modules

2002 EPEP | Electrical Performance of Electronic Packaging
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RDRAM@ Channel Design with 32-bit 4.8GB/s Memory Modules

2002 Electrical Performance of Electronic Packaging
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Physical layer design of a 1.6 GB/s DRAM bus

1999 EPEP | Electrical Performance of Electronic Packaging
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A 2.6 GB/s multi-purpose chip-to-chip interface

1998 ISSCC | International Solid-State Circuits Conference
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