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Douglas F. Pastorello
Douglas F. Pastorello
Silicon Labs
Electronic engineering
Computer science
Phase detector
Delta-sigma modulation
Clock recovery
3
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11
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A Fractional-N PLL for SONET-Quality Clock-Syntlhesis Applicationis
2007
ISSCC | International Solid-State Circuits Conference
Axel Thomsen
Ligang Zhang
Doug Frey
Q. Yu
Lizhong Sun
Akhil K. Garlapati
Ronald B. Hulfachor
Douglas F. Pastorello
Richard J. Juhn
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Citations (1)
A 2.5-Gb/s multi-rate-0.25-μm CMOS clock and data recovery circuit utilizing a hybrid analog/digital loop filter and all-digital referenceless frequency acquisition
2006
ISSCC | International Solid-State Circuits Conference
Michael H. Perrott
Yunteng Huang
Rex T. Baird
Bruno W. Garlepp
Douglas F. Pastorello
Eric King
Qicheng Yu
Dan B. Kasha
Philip David Steiner
Ligang Zhang
Jerrell P. Hein
Bruce P. Del Signore
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A 2.5-Gb/s multi-rate-0.25-μm CMOS clock and data recovery circuit utilizing a hybrid analog/digital loop filter and all-digital referenceless frequency acquisition
2006
ISSCC | International Solid-State Circuits Conference
Michael H. Perrott
Yunteng Huang
Rex T. Baird
Bruno W. Garlepp
Douglas F. Pastorello
Eric King
Qicheng Yu
Dan B. Kasha
Philip David Steiner
Ligang Zhang
Jerrell P. Hein
Bruce P. Del Signore
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Citations (10)
1