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Katsuhiko Ichinose
Katsuhiko Ichinose
Hitachi
Electronic engineering
Optoelectronics
Transistor
CMOS
Physics
4
Papers
60
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Quantifying yield impact of polishing induced defect on the silicon surface
2009
ASMC | Advanced Semiconductor Manufacturing Conference
Hideo Ohta
Sanghyun Lee
Tetsuya Watanabe
Sung Ki Park
Byeong-Sam Moon
Jeong Hoon An
Katsuhiko Ichinose
Jea-Gun Park
Kwon Hong
Kazunori Nemoto
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Metrology of LER: influence of line-edge roughness (LER) on transistor performance
2004
Atsuko Yamaguchi
Katsuhiko Ichinose
Satoshi Shimamoto
Hiroshi Fukuda
Ryuta Tsuchiya
Kazuhiro Ohnishi
Hiroki Kawada
Takashi Iizumi
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A highly dense, high-performance 130 nm node CMOS technology for large scale system-on-a-chip applications
2000
IEDM | International Electron Devices Meeting
Fumio Ootsuka
S. Wakahara
Katsuhiko Ichinose
A. Honzawa
S. Wada
H. Sato
T. Ando
Hiroyuki Ohta
K Watanabe
Takahiro Onai
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0.1-/spl mu/m CMOS technology for high-speed logic and system LSIs with SiO/SiN/poly-Si/W gate-system
1999
IEDM | International Electron Devices Meeting
Takahiro Onai
Shimpei Tsujikawa
Takashi Uchino
Ryuta Tsuchiya
K. Ohnishi
Hiroshi Fukuda
Digh Hisamoto
Naoki Yamamoto
Jiro Yugami
Katsuhiko Ichinose
Fumio Ootsuka
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