Old Web
English
Sign In
Acemap
>
authorDetail
>
Manabu Ichinose
Manabu Ichinose
Electronic circuit
Amplifier
CAS latency
Instruction prefetch
Parallel computing
1
Papers
4
Citations
0.00
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (1)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
An eight-bit prefetch circuit for high-bandwidth DRAM's
1997
IEEE Journal of Solid-state Circuits
Toshio Sunaga
Koji Hosokawa
Yutaka Nakamura
Manabu Ichinose
Yasuyuki Igarashi
Show All
Source
Cite
Save
Citations (4)
1