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Paul A. Bunce
Paul A. Bunce
IBM
Computer science
Electronic engineering
Static random-access memory
Chip
Parallel computing
5
Papers
48
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7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor
2013
ISSCC | International Solid-State Circuits Conference
John D. Davis
Paul A. Bunce
Diana M. Henderson
Yuen H. Chan
Uma Srinivasan
Daniel Rodko
Pradip Patel
Thomas J. Knips
Tobias Werner
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Citations (3)
Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System
2012
IEEE Journal of Solid-state Circuits
James D. Warnock
Yiu-Hing Chan
Sean M. Carey
Huajun Wen
Patrick J. Meaney
Guenter Gerwig
Howard H. Smith
Yuen H. Chan
John S. Davis
Paul A. Bunce
Antonio R. Pelella
Daniel Rodko
Pradip Patel
Thomas Strach
Doug Malone
Frank Malgioglio
José Luis Neves
David L. Rude
William V. Huott
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Citations (27)
A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor
2006
ISSCC | International Solid-State Circuits Conference
John S. Davis
Donald W. Plass
Paul A. Bunce
Y.H. Chan
Antonio R. Pelella
Rajiv V. Joshi
A. Chen
William V. Huott
Thomas J. Knips
Pradip Patel
K. Lo
E. Fluhr
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Citations (17)
Design validation of .18 /spl mu/m 1 GHz cache and register arrays
2000
CICC | Custom Integrated Circuits Conference
D. Malone
Paul A. Bunce
J. DellaPietro
John D. Davis
James W. Dawson
Thomas J. Knips
Donald W. Plass
P. Pritzlaff
Kenneth J. Reyer
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Citations (1)
Directory and Trace memory chip with active discharge cell
1992
Ibm Journal of Research and Development
Paul A. Bunce
William Benedict Chin
Leo James Clark
Barry Watson Krumm
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