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Rajesh Pamula
Rajesh Pamula
University of Washington
Computer science
Electronic engineering
CMOS
Microprocessor
Voltage
5
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A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS
2021
ISSCC | International Solid-State Circuits Conference
Chi-Hsiang Huang
Xun Sun
Yidong Chen
Rajesh Pamula
Arindam Mandal
Visvesh S. Sathe
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A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation
2021
CICC | Custom Integrated Circuits Conference
Arindam Mandal
Diego Peña
Rajesh Pamula
Karam Khateeb
Logan Murphy
Azadeh Yazdan-Shahmorad
Steve I. Perlmutter
Forrest Pape
Jacques C. Rudell
Visvesh S. Sathe
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Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS
2020
VLSIC | Symposium on VLSI Circuits
Xun Sun
Akshat Boora
Rajesh Pamula
Chi-Hsiang Huang
Diego Pena-Colaiocco
Visvesh S. Sathe
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UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS
2020
VLSIC | Symposium on VLSI Circuits
Xun Sun
Akshat Boora
Rajesh Pamula
Chi-Hsiang Huang
Diego Pena-Colaiocco
Visvesh S. Sathe
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Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS
2019
IEEE Journal of Solid-state Circuits
Fahim ur Rahman
Rajesh Pamula
Visvesh S. Sathe
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