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Daehyeon Kwon
Daehyeon Kwon
Samsung
Electronic engineering
Phase noise
Phase-locked loop
CMOS
Electrical engineering
3
Papers
47
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24.8 A 14nm fractional-N digital PLL with 0.14ps rms jitter and −78dBc fractional spur for cellular RFICs
2017
ISSCC | International Solid-State Circuits Conference
Chih-Wei Yao
Wing Fai Loke
Ronghua Ni
Yongping Han
Haoyang Li
Kunal Godbole
Yongrong Zuo
Sangsoo Ko
Nam-Seog Kim
Sang-Wook Han
Ikkyun Jo
Joon-hee Lee
Juyoung Han
Daehyeon Kwon
Chul-Ho Kim
Shinwoong Kim
Sang Won Son
Thomas Byunghak Cho
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Citations (12)
Digital PLL design challenges for cellular RFICs
2017
RFIT | International Symposium on Radio-Frequency Integration Technology
Sangsoo Ko
Chih-Wei Yao
Joon-hee Lee
Sang-Wook Han
Daehyeon Kwon
Wing Fai Loke
Ronghua Ni
Thomas Byunghak Cho
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Citations (0)
A 14-nm 0.14-ps rms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration
2017
IEEE Journal of Solid-state Circuits
Chih-Wei Yao
Ronghua Ni
Chung Lau
Wanghua Wu
Kunal Godbole
Yongrong Zuo
Sangsoo Ko
Nam-Seog Kim
Sang-Wook Han
Ikkyun Jo
Joon-hee Lee
Juyoung Han
Daehyeon Kwon
Chul-Ho Kim
Shinwoong Kim
Sang Won Son
Thomas Byunghak Cho
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Citations (35)
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