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E. R. Hsieh
E. R. Hsieh
Stanford University
Electronic engineering
Engineering
Electrical engineering
Resistive random-access memory
Architecture
3
Papers
16
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Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era
2019
VLSIT | Symposium on VLSI Technology
E. R. Hsieh
H.W. Wang
Chuan Hsi Liu
Steve S. Chung
T. P. Chen
S. A. Huang
T. J. Chen
Osbert Cheng
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A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 1012 Endurance
2019
VLSIT | Symposium on VLSI Technology
E. R. Hsieh
Hsiao-Chun Chang
Steve S. Chung
T. P. Chen
S. A. Huang
T. J. Chen
Osbert Cheng
S. Simon Wong
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High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning
2019
IEDM | International Electron Devices Meeting
E. R. Hsieh
Xin Zheng
M Nelson
Binh Q. Le
Hon-Sum Philip Wong
Subhasish Mitra
S. Simon Wong
M. Giordano
B. Hodson
A. Levy
S.K. Osekowsky
R.M. Radway
Y.C. Shih
W. Wan
Tony F. Wu
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Citations (15)
1