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D. Pandini
D. Pandini
STMicroelectronics
Very-large-scale integration
Electronic engineering
Interconnection
Digital electronics
Time domain
5
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9
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Preface: Proceedings of Second International Conference on Advances in System Testing and Validation Lifecycle (VALID) 2010
2010
A. Alimohammad
A. Baruzzo
L. du Bousquet
P. Dini
H Muccini
A. Klaus
Juho Perälä
D. Pandini
R. Senguttuvan
A. Sinha
A. Stefanescu
B. Vermeulen
S. Van Baelen
H-G. Gross
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Design solutions for the interconnection parasitic effects in deep sub-micron technologies
2000
Microelectronic Engineering
L. Baldi
B. Franzini
R. Zafalon
D. Pandini
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Reduced order macromodel of coupled interconnects for timing and functional verification of sub-half-micron IC designs
1998
ASP-DAC | Asia and South Pacific Design Automation Conference
D. Pandini
P. Scandelara
C. Guardiani
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A moment matching based methodology for crosstalk analysis
1996
ASICON | International Conference on ASIC
D. Pandini
C. Guardiani
P. Gubian
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Optimum CMOS stack generation with analog constraints
1995
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems
E. Malavasi
D. Pandini
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