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Kameswaran Vengattaramane
Kameswaran Vengattaramane
Katholieke Universiteit Leuven
Electronic engineering
Computer science
CMOS
Electrical engineering
Phase-locked loop
10
Papers
225
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A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration
2011
ESSCIRC | European Solid-State Circuits Conference
Kameswaran Vengattaramane
Jonathan Borremans
Michiel Steyaert
Jan Craninckx
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Citations (6)
A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS
2010
ISSCC | International Solid-State Circuits Conference
Jonathan Borremans
Kameswaran Vengattaramane
Vito Giannini
Jan Craninckx
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Citations (12)
A 2-mm $^{2}$ 0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS
2009
IEEE Journal of Solid-state Circuits
Vito Giannini
Pierluigi Nuzzo
C. Soens
Kameswaran Vengattaramane
Julien Ryckaert
Michael Goffioul
Bjorn Debaillie
Jonathan Borremans
J. Van Driessche
Jan Craninckx
Mark Ingels
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Citations (98)
Analysis of fractional spur reduction using ΣΔ-noise cancellation in digital-PLL
2009
ISCAS | International Symposium on Circuits and Systems
Kameswaran Vengattaramane
Jan Craninckx
Michiel Steyaert
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Citations (2)
A gated ring oscillator based parallel-TDC system with digital resolution enhancement
2009
A-SSCC | Asian Solid-State Circuits Conference
Kameswaran Vengattaramane
Jonathan Borremans
Michiel Steyaert
Jan Craninckx
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Citations (4)
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