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Hiroto Yasuura

Kyoto University

29

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120

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Area Efficient High Speed and Low Power MAC Unit

2013
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Functional information extraction from combinational circuits

1991 Electronics and Communications in Japan Part Iii-fundamental Electronic Science
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Locally computable coding for unary operations

1991 CONCUR | International Conference on Concurrency Theory
- Hiroto Yasuura
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Functional memory type parallel processor architecture for solving combinational problems

1990
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Extraction of functional information from combinational circuits

1990 ICCAD | International Conference on Computer Aided Design
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NES: the behavioral model for the formal semantics of a hardware design language UDL/I

1990 DAC | Design Automation Conference
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Semantics of a HIardware Design Language for

1989
- Hiroto Yasuura
- Nagisa Ishiura
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Semantics of a Hardware Design Language for Japanese Standardization

1989 DAC | Design Automation Conference
- Hiroto Yasuura
- Nagisa Ishiura
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Parallel exhaustive search for several NP-complete problems using content addressable memories

1988 ISCAS | International Symposium on Circuits and Systems
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High-Speed Logic Simulation on Vector Processors

1987 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Citations (35)