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D. Sherlekar
D. Sherlekar
Synopsys
Transistor
Electrical engineering
Nano-
Engineering
Electronic engineering
3
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11
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Can We Ever Get to a 100 nm Tall Library? Power Rail Design for 1nm Technology Node
2020
VLSIT | Symposium on VLSI Technology
Victor Moroz
X. W. Lin
P. Asenov
D. Sherlekar
Munkang Choi
B. Cheng
S. Parikh
Po-Wen Chan
J. J. Lee
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DTCO Launches Moore’s Law Over the Feature Scaling Wall
2020
IEDM | International Electron Devices Meeting
Victor Moroz
X. W. Lin
P. Asenov
D. Sherlekar
Munkang Choi
L. Sponton
L.S. Melvin
Jaehyun Lee
Binjie Cheng
A. Nannipieri
Jacky Huang
S. Jones
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2nm Node: Benchmarking FinFET vs Nano-Slab Transistor Architectures for Artificial Intelligence and Next Gen Smart Mobile Devices
2019
VLSIT | Symposium on VLSI Technology
Seung Chul Song
Benjamin Colombeau
M. Bauer
Victor Moroz
X. W. Lin
P. Asenov
D. Sherlekar
Munkang Choi
Jacky Huang
B. Cheng
Chidi Chidambaram
S. Natarajan
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Citations (9)
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