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Nilmini Abeyratne

University of Michigan

5

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65

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SMART: STT-MRAM architecture for smart activation and sensing

2019
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Enhancing DRAM Self-Refresh for Idle Power Reduction

2016 ISLPED | International Symposium on Low Power Electronics and Design
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Checkpointing Exascale Memory Systems with Existing Memory Technologies

2016
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Scaling towards kilo-core processors with asymmetric high-radix topologies

2013 HPCA | High-Performance Computer Architecture
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Citations (52)