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A. Wang
A. Wang
Sun Microsystems
Reduced instruction set computing
Computer science
CMOS
Parallel computing
Chip
2
Papers
23
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A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor
2005
ISSCC | International Solid-State Circuits Conference
H. McIntyre
Dennis Wendell
K. J. Lin
Pradeep Kaushik
Suresh Seshadri
A. Wang
V. Sundararaman
Ping Wang
Song Kim
Wen-Jay Hsu
Heechoul Park
G. Levinsky
Jiejun Lu
M. Chirania
Raymond A. Heald
P. Lazar
S Dharmasena
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A 4MB on-chip L2 cache for a 90nm 1.6GHz 64b SPARC microprocessor
2004
ISSCC | International Solid-State Circuits Conference
Dennis Wendell
J. Lin
Pradeep Kaushik
Suresh Seshadri
A. Wang
V. Sundararaman
P. Wang
H. McIntyre
S. Kim
Wen-Jay Hsu
Heechoul Park
G. Levinsky
J. Lu
M. Chirania
Raymond A. Heald
P. Lazar
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Citations (12)
1