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Qi Wang
Qi Wang
Intel
Electronic engineering
Phase-locked loop
Bandwidth (signal processing)
CMOS
Jitter
3
Papers
13
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29.3 80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with Self- Referenced Asynchronous Adaptive Droop Mitigation
2021
ISSCC | International Solid-State Circuits Conference
Praveen Mosalikanti
Qi Wang
Kuan-Yueh James Shen
Mark L. Neidengard
Syed Feruz Syed Farooq
Grossnickle Vaughn J
Nasser A. Kurd
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A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS
2018
IEEE Transactions on Circuits and Systems I-regular Papers
Kuan-Yueh James Shen
Syed Feruz Syed Farooq
Yongping Fan
Khoa Minh Nguyen
Qi Wang
Mark Neidengard
Nasser A. Kurd
Amr Elshazly
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Citations (3)
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