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Martin Gerhardt

Advanced Micro Devices

17

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105

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Multiple Stress Memorization In Advanced SOI CMOS Technologies

2007 VLSIT | Symposium on VLSI Technology
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Improved stress transfer mechanism in an interlayer dielectric by using an additional stress layer on a double bracing coating in a semiconductor device

2007
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Semiconductor device and method for generating the deformation in silicon-based transistors by using implantation techniques for the production of a strain-inducing layer below the channel region

2007
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Improved stress transfer in an interlayer dielectric by using an additional stress layer over a layer of dual strain in a semiconductor device

2007
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Technique for generating the deformation in silicon-based transistors by using implantation techniques for the production of a strain-inducing layer below the channel region

2007
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Method of improving the lithography properties during gate production in semiconductors with a pronounced surface topography

2006
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Process Integration Issues with Spike, Flash and Laser Anneal Implementation for 90 and 65 NM Technologies

2006 RTP | International Conference on Advanced Thermal Processing of Semiconductors
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Sub-50 nm gate length SOI transistor development for high performance microprocessors

2004 Materials Science and Engineering B-advanced Functional Solid-state Materials
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Temperature scaling for 35 nm gate length high-performance CMOS

2004 Materials Science in Semiconductor Processing
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