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Koichiro Minami
Koichiro Minami
NEC
Electronic engineering
Computer science
digital delay locked loop
Architecture
Delay
7
Papers
111
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A 100 Gb/s transceiver with GND-VDD common-mode receiver and flexible multi-channel aligner
2002
ISSCC | International Solid-State Circuits Conference
K. Tanaka
Muneo Fukaishi
M. Takeuchi
Nobuhide Yoshida
Koichiro Minami
Koichi Yamaguchi
Hiroaki Uchida
Y. Morishita
Toshitsugu Sakamoto
Tomoya Kaneko
Masaaki Soda
Masakazu Kurisu
T. Saeki
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Citations (17)
A 1-GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges
2001
IEICE Transactions on Electronics
Koichiro Minami
Masayuki Mizuno
Hiroshi Yamaguchi
Toshihiko Nakano
Yusuke Matsushima
Yoshikazu Sumi
Takanori Sato
Hisashi Yamashida
Masakazu Yamashina
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Citations (2)
A 0.10 /spl mu/m CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO
2001
CICC | Custom Integrated Circuits Conference
Koichiro Minami
Muneo Fukaishi
Masayuki Mizuno
H Onishi
K. Noda
Kiyotaka Imai
Tadahiko Horiuchi
Hiroshi Yamaguchi
Takanori Sato
Kazuyuki Nakamura
Masakazu Yamashina
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Citations (13)
A 1-GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges
2000
International Solid-State Circuits Conference
Koichiro Minami
Masayuki Mizuno
Hiroshi Yamaguchi
Toshihiko Nakano
Yusuke Matsushima
Yoshikazu Sumi
Takanori Sato
Hisashi Yamashida
Masakazu Yamashina
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Citations (2)
A 1 GHz portable digital delay-locked loop with infinite phase capture ranges
2000
ISSCC | International Solid-State Circuits Conference
Koichiro Minami
Masayuki Mizuno
Hiroshi Yamaguchi
Toshihiko Nakano
Yusuke Matsushima
Yoshikazu Sumi
Takanori Sato
Hisashi Yamashida
Masakazu Yamashina
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Citations (31)
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