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Mitsuko Saito
Mitsuko Saito
Keio University
Electronic engineering
Computer science
Electrical engineering
CMOS
Inductive coupling
13
Papers
134
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A 1 TB/s 1 pJ/b 6.4 ${\rm mm}^{2}/{\rm TB/s}$ QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM
2012
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Noriyuki Miura
Mitsuko Saito
Tadahiro Kuroda
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A 2.7Gb/s/mm 2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking
2011
ISSCC | International Solid-State Circuits Conference
Noriyuki Miura
Yasuhiro Take
Mitsuko Saito
Yoichi Yoshida
Tadahiro Kuroda
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Citations (7)
A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking
2010
ISSCC | International Solid-State Circuits Conference
Mitsuko Saito
Noriyuki Miura
Tadahiro Kuroda
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Citations (22)
47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking
2009
CICC | Custom Integrated Circuits Conference
Mitsuko Saito
Yasufumi Sugimori
Yoshinori Kohama
Yoichi Yoshida
Noriyuki Miura
Hiroki Ishikuro
Tadahiro Kuroda
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Citations (11)
An extended XY coil for noise reduction in inductive-coupling link
2009
A-SSCC | Asian Solid-State Circuits Conference
Mitsuko Saito
Kazutaka Kasuga
Tsutomu Takeya
Noriyuki Miura
Tadahiro Kuroda
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Citations (12)
1