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N.P. Jouppi
N.P. Jouppi
Western Digital
Reduced instruction set computing
Electronic engineering
Parallel computing
Central processing unit
Very-large-scale integration
4
Papers
2
Citations
0.01
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A Nanophotonic Interconnect for High-Performance Many-Core Computation
2008
| Symposium on High-Performance Interconnects
R. G. Beausoleil
J Ahn
N. Binkert
Adam Davis
D. Fattal
M. Fiorentino
N.P. Jouppi
M McLaren
C. M. Santori
R. S. Schreiber
Sean M. Spillane
D. Vantrease
Q. Xu
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Available instruction-level parallelism for superscalar and superpipelined machines
1989
ASPLOS | Architectural Support for Programming Languages and Operating Systems
N.P. Jouppi
D.W. Wall
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A unified vector/scalar floating-point architecture
1989
ASPLOS | Architectural Support for Programming Languages and Operating Systems
N.P. Jouppi
J Bertoni
D.W. Wall
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A 20 MIPS sustained 32 b CMOS microprocessor with 64 b data bus
1989
ISSCC | International Solid-State Circuits Conference
N.P. Jouppi
J. Y.-F. Tang
J. Dion
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