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Ivan Bietti

STMicroelectronics

41

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6.3 A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET

2019 ISSCC | International Solid-State Circuits Conference
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Designing Analog IC at University of Pavia

2014 IEEE Solid-state Circuits Magazine
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Session 5 overview / analog: PLLs

2011 ISSCC | International Solid-State Circuits Conference
- Ivan Bietti
- Tsung-Hsien Lin
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Session 13 overview: Frequency & clock synthesis

2010 ISSCC | International Solid-State Circuits Conference
- Ivan Bietti
- Mike Keaveney
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Reconfigurable VCOs and Synthesizers

2007
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Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End

2006 CICC | Custom Integrated Circuits Conference
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A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter

2006 ESSCIRC | European Solid-State Circuits Conference
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A 5mA CMOS FM Front-End with 39 dB IRR and 52 dB Channel Selectivity

2006 ESSCIRC | European Solid-State Circuits Conference
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Wireless multi-standard terminals: system analysis and design of a reconfigurable RF front-end

2006 IEEE Circuits and Systems Magazine
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A 0.86 – 2.4 GHz Fractional Synthesizer with Spur Compensation and Linearization Techniques for Multi-standard Cellular Transceivers

2006
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