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Subramanian Rajagopalan

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8

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28

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2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids

2015 VLSID | International Conference on VLSI Design
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Fixing Double Patterning violations with look-ahead

2014 ASP-DAC | Asia and South Pacific Design Automation Conference
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Automatic design rule correction in presence of multiple grids and track patterns

2013 DAC | Design Automation Conference
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Efficient Analog/RF Layout Closure with Compaction Based Legalization

2009 VLSID | International Conference on VLSI Design
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Cell Swapping Based Migration Methodology for Analog and Custom Layouts

2008 ISQED | International Symposium on Quality Electronic Design
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A 3-dimensional FEM Based Resistance Extraction

2007 VLSID | International Conference on VLSI Design
- Subramanian Rajagopalan
- Shabbir H. Batterywala
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Citations (4)