Old Web
English
Sign In
Acemap
>
authorDetail
>
Jong-Chern Lee
Jong-Chern Lee
SK Hynix
Computer science
Electronic engineering
Dram
Parallel computing
Bandwidth (signal processing)
3
Papers
37
Citations
0.00
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (3)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
High bandwidth memory(HBM) with TSV technique
2016
ISOCC | International SoC Design Conference
Jong-Chern Lee
Jihwan Kim
Kyung-Whan Kim
Young Jun Ku
Dae-Suk Kim
Chun-Seok Jeong
Tae Sik Yun
Hongjung Kim
Ho Sung Cho
Sangmuk Oh
Hyun Sung Lee
Ki Hun Kwon
Dong Beom Lee
Young Jae Choi
Jae-Jin Lee
Hyeon Gon Kim
Jun Hyun Chun
Jonghoon Oh
Seok-Hee Lee
Show All
Source
Cite
Save
Citations (18)
18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface
2016
ISSCC | International Solid-State Circuits Conference
Jong-Chern Lee
Jihwan Kim
Kyung-Whan Kim
Young Jun Ku
Dae-Suk Kim
Chun-Seok Jeong
Tae Sik Yun
Hongjung Kim
Ho Sung Cho
Yeon Ok Kim
Jae Hwan Kim
Jin Ho Kim
Sangmuk Oh
Hyun Sung Lee
Ki Hun Kwon
Dong Beom Lee
Young Jae Choi
Jeajin Lee
Hyeon Gon Kim
Jun Hyun Chun
Jonghoon Oh
Seok-Hee Lee
Show All
Source
Cite
Save
Citations (16)
A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM
2011
A-SSCC | Asian Solid-State Circuits Conference
Jong-Chern Lee
Sin-Hyun Jin
Dae-Suk Kim
Young Jun Ku
Chul Kim
Byung-Kwon Park
Hong-Gyeom Kim
Seong-Jun Ahn
Jae-Jin Lee
Sung Joo Hong
Show All
Source
Cite
Save
Citations (3)
1