Old Web
English
Sign In
Acemap
>
authorDetail
>
Y. Yano
Y. Yano
NEC
Electronic engineering
Reduced instruction set computing
Computer science
Phase-locked loop
Microprocessor
4
Papers
62
Citations
0.00
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (2)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
A 500 MHz, 32 bit, 0.4 /spl mu/m CMOS RISC processor
1994
ISSCC | International Solid-State Circuits Conference
K. Suzuki
Masakazu Yamashina
T. Nakayama
Masanori Izumikawa
Masahiro Nomura
Hiroyuki Igura
H. Heiuchi
Junichi Goto
Toshiaki Inoue
Youichi Koseki
Hitoshi Abiko
E. Okabe
A. One
Y. Yano
Hachiro Yamada
Show All
Source
Cite
Save
Citations (24)
A 500 MHz 32b 0.4 /spl mu/m CMOS RISC processor LSI
1994
ISSCC | International Solid-State Circuits Conference
K. Suzuki
Masakazu Yamashina
T. Nakayama
Masanori Izumikawa
Masahiro Nomura
Hiroyuki Igura
H. Heiuchi
Junichi Goto
Toshiaki Inoue
Youichi Koseki
Hitoshi Abiko
Kazuhiro Okabe
Atsuki Ono
Y. Yano
Hachiro Yamada
Show All
Source
Cite
Save
Citations (3)
1