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H. Igarashi
H. Igarashi
Toshiba
Electrical engineering
Electronic engineering
CMOS
Engineering
MOSFET
3
Papers
22
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A high performance 100 nm generation SOC technology (CMOS IV) for high density embedded memory and mixed signal LSIs
2001
VLSIT | Symposium on VLSI Technology
K. Miyashita
T. Nakayama
A. Oishi
R. Hasumi
M Owada
S. Aota
Y. Okayama
M. Matsumoto
H. Igarashi
T. Yoshida
K. Kasai
Takashi Yoshitomi
Yasuhiro Fukaura
H. Kawasaki
K. Ishimaru
K. Adachi
M. Fujiwara
K. Ohuchi
Mariko Takayanagi
Hisato Oyamatsu
F. Matsuoka
T. Noguchi
Masakazu Kakumu
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Manufacturable and reliable fluorine-doped low-k interlayer dielectric process for high performance logic LSI
1996
VLSIT | Symposium on VLSI Technology
H. Igarashi
Hisato Oyamatsu
M. Kodera
N. Kaji
T. Matsuno
I. Shibata
M. Kinugawa
Masakazu Kakumu
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A high performance MOSFET design with highly controllable gate length and low RC delay multilevel interconnects technology for high speed logic devices
1995
IEDM | International Electron Devices Meeting
Hisato Oyamatsu
K. Kasai
N. Matsunaga
H. Igarashi
Takeshi Yamaguchi
T. Asamura
A. Azuma
Hideki Shibata
M. Kinugawa
Masakazu Kakumu
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Citations (4)
1