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R. Levinger

Intel

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A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS

2021 ISSCC | International Solid-State Circuits Conference
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A 33% Tuning Range Cross-Coupled DCO with “Folded” Common Mode Resonator Covering both 5G MMW Bands in 16-nm CMOS FinFet

2021 EuMIC | European Microwave Integrated Circuits Conference
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A Compact 3.9-4.7 GHz, 0.82 mW All-Digital PLL with 543 fs RMS Jitter in 28 nm CMOS

2019 SiRF | Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems
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X-band NMOS and CMOS Cross-Coupled DCO’s with a “Folded” Common-Mode Resonator Exhibiting 188.5 dBc/Hz FoM with 29.5% Tuning Range in 16-nm CMOS FinFet

2019 RFIC | Radio Frequency Integrated Circuits Symposium
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Citations (6)