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Naoaki Naka
Naoaki Naka
Electronic engineering
Computer science
CMOS
Transceiver
Phase-locked loop
3
Papers
27
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2024
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A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS
2016
VLSIC | Symposium on VLSI Circuits
Hiroki Miyaoka
Futoshi Terasawa
Masahiro Kudo
Hideki Kano
Atsushi Matsuda
Noriaki Shirai
Shigeaki Kawai
Takayuki Shibasaki
Takumi Danjo
Yuuki Ogata
Yasufumi Sakai
Hisakatsu Yamaguchi
Toshihiko Mori
Yoichi Koyanagi
Hirotaka Tamura
Yutaka Ide
Kazuhiro Terashima
Hirohito Higashi
Tomokazu Higuchi
Naoaki Naka
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Citations (1)
A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS
2015
A-SSCC | Asian Solid-State Circuits Conference
Hiroki Miyaoka
Futoshi Terasawa
Masahiro Kudo
Hideki Kano
Atsushi Matsuda
Noriaki Shirai
Shigeaki Kawai
Tomoyuki Arai
Yutaka Ide
Kazuhiro Terashima
Hirohito Higashi
Tomokazu Higuchi
Naoaki Naka
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Citations (2)
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