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yuusuke matunaga

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A Power-aware Post-processing under depth constraint for LUT-based FPGA Technology Mapping

2009
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イニシエーション・インターバルとアロケーションの制約下における総面積最小を目的としたパイプライン・スケジューリング手法

2009
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Multi-Operand Adder Synthesis on FPGAs using Generalized Parallel Counters

2009 Asia and South Pacific Design Automation Conference
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