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D. Masuda
D. Masuda
Shibaura Institute of Technology
Power gating
Reduced instruction set computing
Translation lookaside buffer
Electronic engineering
Real-time computing
2
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6
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0
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Geyser-2: the second prototype CPU with fine-grained run-time power gating
2011
ASP-DAC | Asia and South Pacific Design Automation Conference
Lei Zhao
Daisuke Ikebuchi
Yoshiki Saito
M. Kamata
Naomi Seki
Yu Kojima
Hideharu Amano
Satoshi Koyama
Tatsunori Hashida
Y. Umahashi
D. Masuda
Kimiyoshi Usami
Keiji Kimura
Mitaro Namiki
Seidai Takeda
Hiroshi Nakamura
Masaaki Kondo
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Citations (6)
Geyser-2: the second prototype CPU with fine-grained run-time power gating
2011
ASP-DAC | Asia and South Pacific Design Automation Conference
L. Zhao
D. Ikebuchi
Y. Saito
M. Kamata
N. Seki
Y. Kojima
H. Amano
S. Koyama
T. Hashida
Y. Umahashi
D. Masuda
Kazuoki Usami
K. Kimura
M. Namiki
S Takeda
H. Nakamura
M. Kondo
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1