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Gyu-Seong Cho
Gyu-Seong Cho
SK Hynix
Electronic engineering
Transistor
Communication channel
Logic gate
NAND gate
4
Papers
26
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Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation
2016
IEEE Transactions on Electron Devices
Dae Woong Kwon
Wandong Kim
Do-Bin Kim
Sangho Lee
Joo Yun Seo
Myung Hyun Baek
Ji-Ho Park
Eun-Seok Choi
Gyu-Seong Cho
Sung Kye Park
Jong-Ho Lee
Byung-Gook Park
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Citations (11)
Channel-Stacked NAND Flash Memory With Tied Bit-Line and Ground Select Transistor
2016
IEEE Electron Device Letters
Dae Woong Kwon
Joo Yun Seo
Se Hwan Park
Wandong Kim
Do-Bin Kim
Sangho Lee
Gyu-Seong Cho
Sung Kye Park
Byung-Gook Park
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Citations (1)
Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory
2015
IEEE Electron Device Letters
Dae Woong Kwon
Wandong Kim
Do-Bin Kim
Sangho Lee
Joo Yun Seo
Myung Hyun Baek
Ji-Ho Park
Eun-Seok Choi
Gyu-Seong Cho
Sung Kye Park
Byung-Gook Park
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Citations (9)
Fully integrated and functioned 44nm DRAM technology for 1GB DRAM
2008
VLSIT | Symposium on VLSI Technology
Hyunjin Lee
Dae-Young Kim
Bong-Ho Choi
Gyu-Seong Cho
Sung-Woong Chung
Wansoo Kim
Myoung-Sik Chang
Young-Sik Kim
Jun-Ki Kim
Tae-Kyun Kim
Hyung Hwan Kim
Hae-Jung Lee
Han Sang Song
Sung Kye Park
Jinwoong Kim
Sung Joo Hong
Sung Wook Park
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Citations (5)
1