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Dong-Jin Chang

KAIST

8

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A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration

2021 IEEE Journal of Solid-state Circuits
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A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration

2019 IEEE Journal of Solid-state Circuits
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A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks

2018 IEEE Transactions on Circuits and Systems Ii-express Briefs
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Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC

2017 IEEE Transactions on Circuits and Systems
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A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

2016 IEEE Journal of Solid-state Circuits
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